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mcquerol/direct-digital-frequency-synthesis-systemverilog

SystemVerilog DDFS project on FPGA. Includes LUT design and sine wave generation.

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open beginner issues
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Latest indexed
Aug 13, 2026
Last GitHub push
Dec 18, 2024
License
MIT License
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Dominant language
SystemVerilog
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good first issue

Issues

1 open indexed issue